1. Field of the Invention
This invention relates to a metal oxide semiconductor thin film transistor (MOS thin film transistor), and more particularly to a MOS thin film transistor comprising a polysilicon layer and a SOI structure. The thin film transistor of the present invention is useful particularly as a load device for Static Random Access Memory (SRAM).
2. Description of the Related Art
MOS thin film transistors (called hereunder MOS-TFT) are widely used in large size LSI for LCD (Liquid Crystal Displays) and, as load devices, in Static Random Access Memories (SRAMs). These devices are mainly composed of a polysilicon thin film formed by deposition and therefore have defects of very high density in the film. As a result, leakage current through P-N junction observed in the film is much larger than that obtained in single crystals.
A typical structure of polysilicon MOS-TFT and drain current-gate voltage characteristic (Id-Vgs) thereof are shown in FIGS. 5(a)-(c), wherein S is a source, G is a gate, and D is a drain. Off current (I Off) is defined by the drain current observed at a zero gate voltage (Vgs=0) with a nominal drain-source voltage (Vds=Vdd), and On current (I ON) is defined by the drain current (Id) observed at a nominal gate and drain-source voltage (Vgd=Vds=Vdd).
The OFF current, i.e., leakage current, depends in a complicated way on the recombination-generation mechanism in the drain depletion region. In addition, in polysilicon, or semiconductor films with high level of crystalline defects, this mechanism is enhanced in the depletion region by the drain-gate electric field. The dependence of the OFF current can be represented by the following equation. EQU I.sub.OFF =qkT.pi..sigma.v.sub.th n.sub.i (N.sub.TS /S.sub.g)Wt.sub.p (.sub..epsilon.S Eo/qNd)exp(Em/Eo).nu. [I]
where:
______________________________________ q: Electronic charge .sigma.: Effective capture cross k: Boltzman constant section T: Absolute Temperature V.sub.th : Thermal velocity N.sub.TS : Traps density n.sub.i : Semiconductor intrinsic (eV/cm.sup.2) carrier concentration W: Transistor channel width S.sub.g : Polysilicon grain size .epsilon..sub.s : Dielectric Constant t.sub.p : Polysilicon thickness Nd: Donor concentration Eo: Constant (1 .times. 10.sup.5 V/cm) .nu.: exponent factor (.about.1/2) Em: Depletion layer maximum electric field ______________________________________
The above maximum electric field (Em) can be expressed by EQU Em=E.sub.1 +E.sub.2 EQU E.sub.1 =.sqroot.2qN.sub.eff Vd/.sub..epsilon.S1 EQU E.sub.2 =.alpha.[(Cox/.epsilon..sub.S)(Vgs-Vds-V.sub.FB)]
wherein .alpha. is a fringing field factor (.about.0.5), and C.sub.ox is the transistor gate oxide capacitance per unit area. The effect of the electric field Em is given by the exponential enhancement factor: Fe=exp (Em/Eo).sup..nu., and this exponential dependence with the gate and drain voltages strongly increases the OFF current of the device.
For applications requiring Static Random Access Memory (SRAMs) to operate with battery, it is essential to have a very low standby power dissipation. For this purpose, such a polysilicon PMOS TFT has been proposed as the load device in the SRAM cell as shown in FIGS. 6(a)-(d) being a plan view, a sectional view taken from the line Y--Y', a sectional view taken from the line X--X', and a diagram of the equivalent circuit, respectively. In the Figures, reference numeral 21 shows a first intermediate oxide film, 22 a second intermediate oxide film, 23 a third polysilicon layer, 24 a second polysilicon layer, 25 a first polysilicon layer, 26 a WSi.sub.x layer, and 27 a P-MOS FET, and Q1 to Q6 specific portions constituting the device.
However, for high density memory, with more than 1 Megabit capacity, a 1 .mu.A total standby current should be specified. This requires that the OFF current of the polysilicon PMOS TFT to be less than 0.1 pA. To meet this requirement and in accordance with the equation [I], various attempts have been made for improving the quality of the polysilicon film by using such a growing technique as enabling a film formation with a larger grain size (Sg.about.1 .mu.m). In this respect, a very thin polysilicon film (tp.about.10 nm) has been formed and proposed to use for the device. However, such a film is very difficult to be produced with good reproductivity in mass production.
Another proposal to reduce the OFF current is to apply the drain-offset structure as shown in FIGS. 7(a) and (b). In this case, the TFT channel region must be defined directly by the pattern of a photoresist mask, because the gate electrode is under the TFT channel, or the device body. The problem with this technique is the difficulty to align the channel with the underlying gate electrode, specially in submicron size devices as required in high density SRAM. As illustrated in FIG. 7(c), supposing the bulk NMOS transistor of being minimum channel length (Ln), the alignment tolerance is approximately DM=Ln/2. That is, the channel length of the polysilicon PMOS transistor, under the gate (GP), will vary between 0 and Ln (See FIGS. 7(d) and (e)).
Also, an LDD (Lightly Doped Drain) structure with source and drain-offset (R.sub.s and R.sub.d as shown in FIGS. 8(a) and (b)) is proposed to reduce OFF current and improve the ON/OFF ratio. This structure is symmetric, in the sense that both the source and drain are lightly doped regions. However, this creates a series resistance with the source electrode which reduces the transistor drain ON current.